In power semiconductor devices, achieving the highest breakdown voltage simultaneously with minimal on-resistance is one of the most important performance characteristics. Lateral geometry devices, such as field-effect transistors (FETs), including metal oxide semiconductor FETs (MOSFETs), metal semiconductor FETs (MESFETs), high electron mobility transistors (HEMTs), etc., have a channel aligned along the semiconductor surface, and which is often located close to the semiconductor surface. If the space-charge (depletion) region occupies only a portion of the gate-drain spacing, the electric field in that spacing is strongly non-uniform and can result in premature breakdown, which limits the device performance. Due to a high carrier concentration in the channel and the close vicinity of the channel to the semiconductor surface, efficient control over the space charge distribution in the gate-drain spacing is extremely challenging.
FIG. 1A shows a conventional heterostructure FET (HFET) 2A according to the prior art, and FIG. 2 shows an illustrative electric field distribution chart according to the prior art. As illustrated in FIG. 2, the electric field profile in the gate-drain spacing having a distance, LGD, shown in FIG. 1A exhibits a strong peak near the gate edge when the HFET 2A is operated as a switch (without a field plate). The peak width is defined by the carrier concentration in the channel. To this extent, a breakdown voltage for the HFET 2A does not increase when the gate-drain spacing distance LGD is increased.
One approach to lower the peak electric field near the gate edge is the use of one or more field-modulating plates (FPs), which can be connected to either the gate, source, or drain electrodes. FIG. 1B shows a conventional heterostructure FET (HFET) 2B including a field plate FP according to the prior art. A multistep field plate structure is shown in FIG. 1C, and a gradual field plate structure is shown in FIG. 1D. As illustrated in FIG. 2, the field plate structure decreases the peak field near the gate electrode edge by splitting it into two peaks, thereby increasing the breakdown voltage for the device. However, even the multiple field plate structures, which split the electric field into even more peaks, cannot achieve a uniform electric field in the device channel.
Additionally, optimal configuration of multiple field plates is difficult to achieve. For example, the optimal configuration requires precisely controlled field plate length and dielectric thickness variation along the channel. In addition, prior art field plates have either source or gate potential applied to them, and therefore, significant voltage exists between the field plate and the drain electrode. As a result, a device including field plate(s) can suffer from premature breakdown between the field plate(s) and the drain electrode. Furthermore, the field plate(s) increases the inter-electrode and electrode-semiconductor capacitances, and therefore, decreases the device maximum operating frequency.
As a result of the above limitations, current high-voltage FET switches (i) do not achieve the breakdown voltages predicted by fundamental material properties and (ii) exhibit breakdown voltage—gate-drain spacing dependence saturating at high voltages, typically four hundred volts and above, which imposes serious limitations on device design for kilovolt switching applications.